This invention relates to a data processing system for use in processing a plurality of data arrays each of which consists of a great number of data elements.
Recently, a very high speed computer (so-called a super computer) has become indispensable to simulation in weather forecasting and nuclear engineering and to image processing for resource search and the like. Such a super computer should have a high speed in processing each data array, each data sequence consisting of a great number of data elements, such as vectors.
A conventional data processing system disclosed by S. R. Cray, Jr., U.S. Pat. No. 4,128,880 is operable as such a super computer for successively accessing each data array of vectors and comprises a plurality of vector registers coupled to a memory, a plurality of functional units cooperating with the vector registers, and a control unit for controlling the vector registers. Operation is mainly carried out between the vector registers and the functional units under control of the control unit, rather than between the memory and the vector registers. With this structure, it is possible to calculate or process the vectors at a high speed by the use of the vector registers when the vectors are memorized in the vector registers. However, the vectors are now always stored in the vector registers because each data array requires a great number of addresses.
Although the memory should inevitably be accessed in the absence of a data array in the vector registers, no suggestion is offered by the above-referenced patent. In the absence, throughput of the system is inevitably degraded and governed by throughput between the memory and the vector registers when the memory is accessed in a usual manner.
In order to raise the throughput, a virtual access method may be considered which carries out adress translation by the use of an address translation buffer. However, the address translation buffer should have a great capacity in order to deal with such a data array widely interspersed in the memory.